TL;DR

Lead Design Engineer (Physical Design): Focusing on high-speed digital DDR and HBM IP physical implementation, enhancing current PD design flow with necessary scripts and tools. Focus on solving design issues, analyzing PPA optimization methodologies, and implementing optimal design parameters for different projects.

Location: Onsite in Beijing

Company

Cadence hires and develops leaders and innovators who want to make an impact on the world of technology.

What you will do

  • Focus on high-speed digital DDR and HBM IP physical implementation.
  • Develop necessary scripts or tools to enhance current PD design flow.
  • Complete project tasks.
  • Solve design issues and provide flow to check and avoid similar issues.
  • Analyze and summarize PPA optimization methodologies and results.
  • Implement optimal design parameters and flows for different projects.

Requirements

  • MS in EE with at least 3 years of relevant IC design experience.
  • Good physical design experience in the digital implementation domain including Floorplan, CTS, STA, Physical verification, Power analysis.
  • Solid background in circuits, electronics, physics, and willingness to learn new technology for cutting edge process node and advanced design methodology.
  • Skilled in scripting languages, such as Perl, C shell, TCL, Makefile, and Python.
  • Familiar with EDA tools like Innovus, ICC, Calibre, Tempus, and PrimeTime.

Culture & Benefits

  • Work on high-performance products based on the industry’s advanced technology with high frequencies up to 6400MHz.
  • Gain experience with TSMC 3nm/5nm/7nm/12nm and Samsung 4nm/5nm/7nm/8nm/10nm processes.
  • Face great challenges such as FP, CTS, and STA.
  • Get rich experience and advanced methodology.