TL;DR
IP Design Verification Engineer (Silicon): Performing functional verification of IP logic and developing test benches to ensure compliance with microarchitecture specifications. Focus on root-cause debugging, collaboration with RTL and physical design teams, and enhancing verification methodology for complex silicon features.
Location: Must be based in Petah-Tikva, Israel (Hybrid model)
Company
A global leader in silicon and platform engineering, delivering breakthrough computing solutions and next-generation product architectures.
What you will do
- Develop IP verification plans, test benches, and simulation environments.
- Execute verification plans and analyze power and timing metrics.
- Replicate and debug complex issues in the pre-silicon environment.
- Implement corrective measures to resolve failing tests.
- Collaborate with architects and RTL developers to improve verification quality.
- Document test plans and drive technical reviews with cross-functional teams.
Requirements
- B.Sc. or M.Sc. in Electrical or Computer Engineering.
- Minimum 6+ years of experience in pre-silicon verification.
- Experience in verification at block, cluster, and FC levels.
- Strong proficiency in Specman “e” and SystemVerilog.
- Understanding of verification methodologies and debugging techniques.
- Experience working directly with architecture, RTL, and physical design teams.
Nice to have
- Knowledge of PCIe protocols.
Culture & Benefits
- Hybrid work model allowing for split time between on-site and off-site work.
- Opportunity to contribute to next-generation silicon and platform solutions.
- Exposure to industry-leading design verification infrastructure.